1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which a source/drain region occupies a reduced area so as to decrease the parasitic capacitance and parasitic resistance of the source/drain region, as well as a method for producing the same.
2. Description of the Related Art
In general, smaller insulation gate type field effect transistors (FETs) become more susceptible to problems such as fluctuation in the threshold voltage due to variation in the gate length caused by processing variation, an increased off-leak current due to deterioration of subthreshold characteristics, and deterioration of transistor characteristics due to short channel effects, e.g., so-called punch-through.
One method for solving such problems has been to reduce the junction depth of the source/drain regions adjoining a channel region of a transistor. A reduced junction depth can be realized by, for example, a structure in which source/drain regions (stacked diffusion layers) are stacked on both sides of a gate electrode so as to be located above the channel region via gate electrode lateral wall insulation films.
FIGS. 22A, 22B, and 22C are cross-sectional views illustrating steps of a conventional method for forming stacked diffusion layers.
As shown in FIG. 22A, a gate electrode 1005 whose upper face and side walls are covered with an insulation film 1006 is formed upon a semiconductor wafer 1001, with a gate insulation film 1004 interposed therebetween. The semiconductor wafer 1001 generally includes an active region 1003 (composed of a silicon substrate) and device separation regions 1002 (composed of a silicon oxide film).
Next, as shown in FIG. 22B, a selective epitaxial growth method is used to grow a silicon film 1007 exclusively in regions (source/drain regions) where the silicon surface is exposed, thereby forming stacked diffusion layer regions (which are composed of a semiconductor) in the source/drain regions. A selective epitaxial growth method is disclosed in Japanese Laid-open Publication No. 61-196577.
As shown in FIG. 22C, an interlayer insulation film 1008 is formed, and upper wiring 1010 is coupled to the source/drain regions 1007 via contact wires 1009.
After the silicon film (epitaxial silicon, polycrystalline silicon, etc.) has been formed above the channel region, impurity ions are implanted so as to form the source/drain regions. By thus implanting impurity ions in the stacked silicon films which are located above the channel region, it becomes possible to reduce the junction depth of the source/drain region impurity diffusion layers relative to the channel region of the transistor. As a result, so-called short channel effects can be effectively prevented.
The, source/drain regions 1007 extend from the gate electrode 1005 to the device separation regions 1002 along a direction X-X' (commonly referred to as the "gate length direction") which is perpendicular to the longitudinal direction of the gate electrode. When contact holes are formed in such source/drain regions 1007, the length of each source/drain region 1007 will be determines as follows.
FIG. 15 is a diagram illustrating the relationship between a gate electrode, an active region, and contact holes. A positioning margin p is provided between the gate electrode and each contact hole. Each contact hole has a width o. The contact holes are positioned with respect to the source/drain regions with a margin q as illustrated in FIG. 15. It will be appreciated that the length of each source/drain region 1007 cannot become smaller than p+o+q in the semiconductor device illustrated in FIG. 22C.
Thus, it is difficult to reduce the area occupied by the source/drain regions in accordance with the semiconductor device disclosed in Japanese Laid-open Publication No. 61-196577.